The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7378340 B1

PDF
Full Text
Expired
Date of Patent:
May. 27, 2008

Filed:

Feb. 03, 2006
Applicants:

Yoshiyuki Enomoto, Kanagawa, JP;

Hiroyuki Kawashima, Kanagawa, JP;

Masaki Okamoto, Kanagawa, JP;

Inventors:

Yoshiyuki Enomoto, Kanagawa, JP;

Hiroyuki Kawashima, Kanagawa, JP;

Masaki Okamoto, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/15 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film. The second-mask forming layer is etched through the fourth mask to thereby form a second mask having the interconnect trench pattern, and the first insulating film that remains under the bottoms of the via holes is removed. Subsequently, the second insulating film is etched through the second mask to thereby form an interconnect trench, and then the second mask is removed.


Find Patent Forward Citations

Enomoto, Yoshiyuki. (2008). Method of manufacturing semiconductor device and semiconductor device (U.S. Patent No. 7378340). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7378340

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