The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Apr. 20, 2005
Applicants:

JO C. Ebergen, San Francisco, CA (US);

George J. Chen, Union City, CA (US);

Inventors:

Jo C. Ebergen, San Francisco, CA (US);

George J. Chen, Union City, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.


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