The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Nov. 18, 2003
Applicants:

Geun-hee Cho, Suwon, KR;

Byung-hoon Jeong, Suwon, KR;

Kyu-hyoun Kim, Suwon, KR;

Inventors:

Geun-Hee Cho, Suwon, KR;

Byung-Hoon Jeong, Suwon, KR;

Kyu-Hyoun Kim, Suwon, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.


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