The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
Apr. 07, 2006
Hung-yan Cheung, San Jose, CA (US);
Michael Y. Zhang, Palo Alto, CA (US);
Hung-Yan Cheung, San Jose, CA (US);
Michael Y. Zhang, Palo Alto, CA (US);
Pericom Semiconductor Corp., San Jose, CA (US);
Abstract
A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback clock that is also applied to the phase detector. An edge-triggered set-reset SR flip-flop generates a duty-cycle-corrected output clock. The SR flip-flop is set by the leading edge of the input clock, but is reset by the trailing edge of the feedback clock. The VCO generates the feedback clock with the desired duty cycle, such as 50%. The leading edge of the output clock is generated by the input clock, avoiding noise generated by the PLL, while the trailing edge of the output clock is generated by the feedback clock and has PLL noise, but corrects for the desired duty cycle.