The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Jun. 14, 2005
Applicants:

Steven P. Young, Boulder, CO (US);

Trevor J. Bauer, Boulder, CO (US);

Manoj Chirania, Palo Alto, CA (US);

Venu M. Kondapalli, Sunnyvale, CA (US);

Inventors:

Steven P. Young, Boulder, CO (US);

Trevor J. Bauer, Boulder, CO (US);

Manoj Chirania, Palo Alto, CA (US);

Venu M. Kondapalli, Sunnyvale, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.


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