The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Sep. 07, 2005
Applicants:

Hiroyuki Kutsukake, Yokohama, JP;

Yasuhiko Matsunaga, Yokohama, JP;

Shoichi Miyazaki, Yokohama, JP;

Inventors:

Hiroyuki Kutsukake, Yokohama, JP;

Yasuhiko Matsunaga, Yokohama, JP;

Shoichi Miyazaki, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a semiconductor substrate having a first surface. First gate electrodes are formed along a first direction on the first surface. Source/drain areas are formed in the first surface and sandwich a channel region. A first interlayer insulating layer fills a region between the first gate electrodes and has the top lower than the tops of the first gate electrodes. A second interlayer insulating layer is formed above the first gate electrodes and the first interlayer insulating layer. Interconnect layers are formed in the second interlayer insulating layer along a direction which intersects the first direction and is insulated from each other. A region between the interconnect layers is filled with the second interlayer insulating layer. A contact plug is formed in the first and second interlayer insulating layers and is in contact with the interconnect layer and the source/drain area.


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