The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Jan. 24, 2003
Applicant:

Axel Hülsmann, Freiburg, DE;

Inventor:

Axel Hülsmann, Freiburg, DE;

Assignee:

MergeOptics GmbH, Berlin, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a heterobipolar transistor, comprising an emitter which includes a first semiconductor layer () made of a first semiconductor material and a second semiconductor layer () made of a second semiconductor material, a band gap value of the first semiconductor material being smaller than a band gap value of the second semiconductor material. A semiconductor intermediate layer () made of an intermediate layer semiconductor material is disposed between the first semiconductor layer () and the second semiconductor layer () and a band gap value of the intermediate layer semiconductor material is greater than the band gap value of the first semiconductor material and smaller than the band gap value or the second semiconductor material. A potential barrier forms at the interface between two semiconductor materials having different band gap values and a stream of electrons must tunnel through it. It is easier for electrons jointly to tunnel through the energy barriers occurring at the interfaces of the semiconductor intermediate layer () than to tunnel through one energy barrier forming at an interface between the first semiconductor layer () and the second semiconductor layer () without an energy barrier generating semiconductor intermediate layer positioned between them. The resistance of the heterobipolar transistor emitter arrangement thus in lowered by the invention.


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