The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2008
Filed:
May. 12, 2005
Venkatesan Manivannan, Rexford, NY (US);
Abasifreke Udo Ebong, Marietta, GA (US);
Jiunn-ru Jeffrey Huang, Schenectady, NY (US);
Thomas Paul Feist, Niskayuna, NY (US);
James Neil Johnson, Schenectady, NY (US);
Venkatesan Manivannan, Rexford, NY (US);
Abasifreke Udo Ebong, Marietta, GA (US);
Jiunn-Ru Jeffrey Huang, Schenectady, NY (US);
Thomas Paul Feist, Niskayuna, NY (US);
James Neil Johnson, Schenectady, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A photovoltaic device comprising a photovoltaic cell is provided. The photovoltaic cell includes an emitter layer comprising a crystalline semiconductor material and a lightly doped crystalline substrate disposed adjacent the emitter layer. The lightly doped crystalline substrate and the emitter layer are oppositely doped. Further, the photovoltaic device includes a back surface passivated structure coupled to the photovoltaic cell. The structure includes a highly doped back surface field layer disposed adjacent the lightly doped crystalline substrate. The highly doped back surface field layer includes an amorphous or a microcrystalline semiconductor material, wherein the highly doped back surface field layer and the lightly doped crystalline substrate are similarly doped, and wherein a doping level of the highly doped back surface field layer is higher than a doping level of the lightly doped crystalline substrate. Additionally, the structure may also include an intrinsic back surface passivated layer disposed adjacent the lightly doped crystalline substrate, where the intrinsic back surface passivated layer includes an amorphous or a microcrystalline semiconductor material.