The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Feb. 03, 2006
Applicants:

John Michael Hergenrother, Ridgefield, CT (US);

Zhibin Ren, Hopewell Junction, NY (US);

Dinkar Virendra Singh, White Plains, NY (US);

Jeffrey William Sleight, Ridgefield, CT (US);

Inventors:

John Michael Hergenrother, Ridgefield, CT (US);

Zhibin Ren, Hopewell Junction, NY (US);

Dinkar Virendra Singh, White Plains, NY (US);

Jeffrey William Sleight, Ridgefield, CT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.


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