The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2008

Filed:

Jun. 02, 2005
Applicants:

Srinivasan K. Ganapathi, Fremont, CA (US);

Keith T. Deconde, San Jose, CA (US);

Randolph S. Gluck, San Jose, CA (US);

Inventors:

Srinivasan K. Ganapathi, Fremont, CA (US);

Keith T. DeConde, San Jose, CA (US);

Randolph S. Gluck, San Jose, CA (US);

Assignee:

Fidelica Microsystems, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01D 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A sensor for a textured surface (e.g., a fingerprint) is provided. The sensor includes a flexible substrate and a flexible membrane supported above the substrate by one or more spacers. The sensor also includes multiple pressure sensor elements responsive to a separation between parts of the membrane and corresponding parts of the substrate. The membrane is conformable to the textured surface being sensed, so the variation in separation between substrate and membrane is representative of the textured surface being sensed. A preferred sensor array arrangement has a set of parallel substrate electrodes on the substrate facing the membrane and a set of parallel membrane electrodes on the membrane facing the substrate, where the substrate and membrane electrodes are perpendicular. The sensor array is preferably an entirely passive structure including no active electrical devices, to reduce cost. Row and column addressing circuitry can be provided as separate units (e.g., ASIC chips) to be hybrid integrated with the sensor array.


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