The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Aug. 11, 2004
Jinyong Yuan, Cupertino, CA (US);
Gregg William Baeckler, San Jose, CA (US);
James G Schleicher, Ii, Los Gatos, CA (US);
Michael Hutton, Mountain View, CA (US);
Jinyong Yuan, Cupertino, CA (US);
Gregg William Baeckler, San Jose, CA (US);
James G Schleicher, II, Los Gatos, CA (US);
Michael Hutton, Mountain View, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.