The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Feb. 17, 2004
William E. Dougherty, Jr., Pleasant Valley, NY (US);
Victor Kravets, White Plains, NY (US);
Prabhakar N. Kudva, New York, NY (US);
Andrew J. Sullivan, Wappinger Falls, NY (US);
William E. Dougherty, Jr., Pleasant Valley, NY (US);
Victor Kravets, White Plains, NY (US);
Prabhakar N. Kudva, New York, NY (US);
Andrew J. Sullivan, Wappinger Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Routability (or wiring congestion) in a VLSI chip is becoming increasingly important as chip complexity increases. Congestion has a significant impact on performance, yield, and chip area. The present invention targets the optimization of congestion early in technology independent synthesis prior to physical design. Instead of attempting to optimize the logic structure as well as the spatial placement of a circuit, we pose a more modest goal limiting such optimization to the scope of logic synthesis. That is, we propose an aggressive optimization approach that is cognizant of circuit structure during technology independent synthesis and produces more predictable implementations which give better routability and yield.