The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2008

Filed:

Feb. 16, 2005
Applicants:

Hugh S O, Fremont, CA (US);

Chih-ching Shih, Pleasanton, CA (US);

Cheng-hsiung Huang, Cupertino, CA (US);

Yow-juang B LU, San Jose, CA (US);

Inventors:

Hugh S O, Fremont, CA (US);

Chih-Ching Shih, Pleasanton, CA (US);

Cheng-Hsiung Huang, Cupertino, CA (US);

Yow-Juang B Lu, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors ('TFTs') for the pull-up and pull-down transistors, and well as for the pass-gates. These TFTs preferably include features such as ion implants and a dielectric with a high dielectric constant 'K.' In addition to reducing soft errors and cell leakage, the invention preferably provides other benefits such as low cell area and scalability.


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