The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2008
Filed:
Apr. 13, 2005
John Armer, Middlesex, NJ (US);
Markus Paul Josef Mergens, Ravensburg, NJ (US);
Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);
Cornelius Christian Russ, Diedorf, DE;
John Armer, Middlesex, NJ (US);
Markus Paul Josef Mergens, Ravensburg, NJ (US);
Phillip Czeslaw Jozwiak, Plainsboro, NJ (US);
Cornelius Christian Russ, Diedorf, DE;
Sarnoff Corporation, Princeton, NJ (US);
Sarnoff Europe, Gistel, BE;
Abstract
An electrostatic discharge (ESD) protection circuit for a semiconductor integrated circuit (IC) that protects core circuitry of the IC during normal operations, and shunts ESD events during non-powered mode of the IC. The ESD protection circuitry includes a multi-fingered MOS transistor, each finger respectively adapted for coupling between an I/O pad and a first supply line of the IC. An ESD detector is coupled to the I/O pad via a first terminal, and a second terminal is adapted for coupling to a second supply line potential of the IC. A parasitic capacitance is formed between the second supply line potential of the IC and the first supply line potential. A transfer circuit is coupled to a third terminal of the ESD detector and is adapted for biasing at least one gate respectively associated with at least one finger of the multi-fingered MOS transistor.