The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7372251 B1

PDF
Full Text
Expired
Date of Patent:
May. 13, 2008

Filed:

Jun. 02, 2005
Applicant:

Osamu Ichikawa, Takatsuki, JP;

Inventor:

Osamu Ichikawa, Takatsuki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit has a memory operating on a first clock. A memory device captures first output data, being output from the memory in synchronization with the first clock, depending on a second clock having a frequency equal to or less than the first clock. An expected value comparison section, operating on the second clock, compares second output data being output from the memory device and third output data being output from the memory immediately after the output of the first output data with a predetermined expected value.


Find Patent Forward Citations

Ichikawa, Osamu. (2008). Semiconductor integrated circuit and memory test method (U.S. Patent No. 7372251). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7372251

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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