The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2008

Filed:

May. 05, 2003
Applicants:

Jean-jen Cheng, Taipei, TW;

Pei-sung Chuang, Taipei Hsien, TW;

Inventors:

Jean-Jen Cheng, Taipei, TW;

Pei-Sung Chuang, Taipei Hsien, TW;

Assignee:

Alcor Micro, Corp., Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention discloses an integrated circuit anti-interference outline structure for applications of integrated circuits capable of shielding the integrated circuit from invasions of external electromagnetic waves and leaks of internal electromagnetic waves, wherein the integrated circuit anti-interference outline structure surrounds a periphery of a partial circuit within the integrated circuit and comprises a plurality of PNP structures. At a surface of the integrated circuits are two metal strips for producing a parasitic capacitance at poly layers in order to control noises within acceptable ranges. On a P-substrate therein is disposed with a deep N-well layer for connecting to an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area, and thus having noise currents overflow from a ground terminal as well as preventing the integrated circuit from invasions and leaks of electromagnetic waves.


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