The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7370132 B1

PDF
Full Text
Expired
Date of Patent:
May. 06, 2008

Filed:

Nov. 16, 2005
Applicants:

Wei Je Huang, Fremont, CA (US);

Luc R. Bisson, San Jose, CA (US);

Oren Rubinstein, Sunnyvale, CA (US);

Michael B. Diamond, Los Gatos, CA (US);

William B. Simms, San Jose, CA (US);

Inventors:

Wei Je Huang, Fremont, CA (US);

Luc R. Bisson, San Jose, CA (US);

Oren Rubinstein, Sunnyvale, CA (US);

Michael B. Diamond, Los Gatos, CA (US);

William B. Simms, San Jose, CA (US);

Assignee:

Nvidia Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.


Find Patent Forward Citations

Huang, Wei. (2008). Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width (U.S. Patent No. 7370132). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7370132

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…