The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2008
Filed:
Aug. 12, 2004
Yoshiyuki Matsunaga, Kamakura, JP;
Shinji Ohsawa, Ebina, JP;
Nobuo Nakamura, Fuchu, JP;
Hirofumi Yamashita, Ota-ku, JP;
Hiroki Miura, Yokohama, JP;
Yoshiyuki Matsunaga, Kamakura, JP;
Shinji Ohsawa, Ebina, JP;
Nobuo Nakamura, Fuchu, JP;
Hirofumi Yamashita, Ota-ku, JP;
Hiroki Miura, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;
Abstract
An MOS-type solid-state imaging apparatus includes an imaging region formed by two-dimensionally arranging unit cells serving as photoelectric conversion portions on a semiconductor substrate, a plurality of vertical address lines arranged in a row direction of the imaging region to select a row of unit cells to be addressed, a plurality of vertical signal lines arranged in a column direction of the imaging region to read out signals from the unit cells in each column, a plurality of load transistors each connected to one end of each of the vertical signal lines, and a plurality of horizontal selection transistors each connected to the other end of each of the vertical signal lines. In this apparatus, each unit cell includes a photodiode serving as a photoelectric conversion portion, an amplification transistor having a gate to which an output from the photodiode is supplied, and a source and a drain respectively connected to the vertical signal line and the vertical address line, an address capacitor connected between the gate of the amplification transistor and the vertical address line, and a reset transistor connected in parallel with the address capacitor.