The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2008
Filed:
Dec. 12, 2003
Fred C. Redeker, Fremont, CA (US);
John Boyd, Atascadero, CA (US);
Yezdi Dordi, Palo Alto, CA (US);
William Thie, Mountain View, CA (US);
Bob Maraschin, Cupertino, CA (US);
Fred C. Redeker, Fremont, CA (US);
John Boyd, Atascadero, CA (US);
Yezdi Dordi, Palo Alto, CA (US);
William Thie, Mountain View, CA (US);
Bob Maraschin, Cupertino, CA (US);
Lam Research Corporation, Fremont, CA (US);
Abstract
Broadly speaking, the present invention provides a method and an apparatus for planarizing a semiconductor wafer ('wafer'). More specifically, the present invention provides for depositing a planarizing layer over the wafer, wherein the planarizing layer serves to fill recessed areas present on a surface of the wafer. A planar member is positioned over and proximate to a top surface of the wafer. Positioning of the planar member serves to entrap electroless plating solution between the planar member and the wafer surface. Radiant energy is applied to the wafer surface to cause a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase in turn causes plating reactions to occur at the wafer surface. Material deposited through the plating reactions forms a planarizing layer that conforms to a planarity of the planar member.