The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Jun. 29, 2005
Applicants:
Prasanna Sundararajan, San Jose, CA (US);
Carter Hamilton, San Jose, CA (US);
Ian L. Mcewen, Golden, CO (US);
Inventors:
Prasanna Sundararajan, San Jose, CA (US);
Carter Hamilton, San Jose, CA (US);
Ian L. McEwen, Golden, CO (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of circuit design for a programmable logic device (PLD) can include identifying a plurality of routing resources, wherein each of the plurality of routing resources is associated with a reliability measure, and selecting routing resources for use in routing a circuit design for the PLD according to, at least in part, the reliability measures. The circuit design for the PLD can be routed using the selected routing resources.