The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Dec. 19, 2005
Takashi Kurihara, Kasugai, JP;
Kenji Wada, Kasugai, JP;
Masahiro Suzuki, Kasugai, JP;
Eiji Fujine, Kasugai, JP;
Takashi Kurihara, Kasugai, JP;
Kenji Wada, Kasugai, JP;
Masahiro Suzuki, Kasugai, JP;
Eiji Fujine, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S(FIG.), the static IR drop is calculated based on the power unit management table CT obtained in Step S