The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2008

Filed:

Sep. 17, 2003
Applicants:

Victor Roberts Augsburg, Cary, NC (US);

Jeffrey Todd Bridges, Raleigh, NC (US);

Michael Scott Mcilvaine, Wake Forest, NC (US);

Thomas Andrew Sartorius, Raleigh, NC (US);

Rodney Wayne Smith, Raleigh, NC (US);

Inventors:

Victor Roberts Augsburg, Cary, NC (US);

Jeffrey Todd Bridges, Raleigh, NC (US);

Michael Scott McIlvaine, Wake Forest, NC (US);

Thomas Andrew Sartorius, Raleigh, NC (US);

Rodney Wayne Smith, Raleigh, NC (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.


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