The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2008

Filed:

Dec. 20, 2001
Applicants:

Benjamin Tang, Hawthorne, CA (US);

Scott Southwell, Dogwood, CA (US);

Nicholas Robert Steffen, Redondo Beach, CA (US);

Inventors:

Benjamin Tang, Hawthorne, CA (US);

Scott Southwell, Dogwood, CA (US);

Nicholas Robert Steffen, Redondo Beach, CA (US);

Assignee:

Primarion, Inc., Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03D 3/24 (2006.01); H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. In particular, a system and method for dual loop data synchronization using a granular FIFO fill level indicator is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL, which represents a fill level of a FIFO. A granular FIFO fill level indicator of the DLL provides input to the phase shifter to adjust the frequency of the PLL accordingly. Thus, the frequency of the data input rate can be controlled and a constant fill level of the FIFO can be maintained. A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.


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