The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Feb. 23, 2005
Sadao Yamashita, Kyoto, JP;
Sadao Yamashita, Kyoto, JP;
Murata Manufacturing Co., Ltd., Kyoto, JP;
Abstract
An FET amplifier includes an FET for amplifying a high-frequency signal to be input to the gate on the basis of a gate bias voltage from a gate bias control circuit. In the FET amplifier, a high-frequency signal input circuit and the output portion of an inverting amplifier are made conductive to the gate of the FET. A voltage stabilizing circuit generating a positive DC constant-voltage signal is made conductive to the non-inverting input portion of the inverting amplifier, and a gate bias control signal input circuit is made conductive to the inverting input portion through an inverter circuit. When the output voltage from the inverter circuit is 0 V, the inverting amplifier outputs a positive gate bias voltage (in the High state) and, when the output voltage from the inverter circuit is a fixed positive voltage, the inverting amplifier outputs a negative gate bias voltage (in the Low state) lower than the pinch-off voltage of the FET. The FET is ON/OFF controlled by the gate bias voltage and pulse modulates the input high-frequency signal to output the signal.