The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2008
Filed:
Sep. 13, 2004
Yaron Kretchmer, Fremont, CA (US);
Fredrik Haghverdian, Sunnyvale, CA (US);
Yaron Kretchmer, Fremont, CA (US);
Fredrik Haghverdian, Sunnyvale, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern may be designed to minimize dishing effects of the interconnects as a result of planarization. Further, the slotting pattern may be designed to minimize resistance in the interconnects. For instance, the slotting pattern may include slots that are staggered, evenly aligned, or a combination of both staggered and evenly aligned. In addition, the slots may be spaced apart such that electrical paths are shorter across the interconnects. By incorporating such interconnects in semiconductor devices, better performing semiconductor devices can be realized.