The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
Aug. 23, 2005
Yu-yen MO, San Jose, CA (US);
Manoj Gopalan, Milpitas, CA (US);
Venkat R. Podduturi, San Jose, CA (US);
Yu-yen Mo, San Jose, CA (US);
Manoj Gopalan, Milpitas, CA (US);
Venkat R. Podduturi, San Jose, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A method for inserting flip-flops in an interconnect is provided such that a cycle time constraint for the interconnect is satisfied. First of all, a flop is inserted at an initial placement at a node along a signal path of the interconnect such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net. Secondly, the initial placement of the flop is optimized such that a delay difference, defined by a downstream delay minus an upstream delay, relative to an optimal placement at a downstream node along the signal path of the net is not greater than zero. The disclosed method can also satisfy the flop stage requirement and/or a minimum number of flops requirement for an interconnect.