The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
Apr. 27, 2005
Ji Park, San Jose, CA (US);
Jinyong Yuan, Cupertino, CA (US);
Kar Keng Chua, Penang, MY;
Evgenii Puchkaryov, Sunnyvale, CA (US);
Ji Park, San Jose, CA (US);
Jinyong Yuan, Cupertino, CA (US);
Kar Keng Chua, Penang, MY;
Evgenii Puchkaryov, Sunnyvale, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method is provided for creating and using a library of known logic elements for facilitating the design of equivalent FPGA, structured ASIC, or other integrated circuits. Each cell in the library corresponds to a circuit element and contains equivalent circuit models of the element for implementation in different integrated circuit technologies. The cells are named and indexed using a library cell key that contains a fixed set of cell properties which uniquely characterize the function of the cell. The cell key can be used to locate cells in the library or in circuit designs, and to verify that the circuit models contained in the cell implement the correct logic function.