The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2008

Filed:

Nov. 18, 2004
Applicants:

Brian David Barrick, Pflugerville, TX (US);

Kimberly Marie Fensler, Round Rock, TX (US);

Dwain Alan Hicks, Pflugerville, TX (US);

David Scott Ray, Georgetown, TX (US);

David Shippy, Austin, TX (US);

Takeki Osanai, Austin, TX (US);

Inventors:

Brian David Barrick, Pflugerville, TX (US);

Kimberly Marie Fensler, Round Rock, TX (US);

Dwain Alan Hicks, Pflugerville, TX (US);

David Scott Ray, Georgetown, TX (US);

David Shippy, Austin, TX (US);

Takeki Osanai, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory address is identified. The load instruction is stored in a miss queue. And the load instruction is tagged as a local miss.


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