The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 22, 2008

Filed:

Sep. 12, 2003
Applicants:

Barry H. Harrison, Nathan, AU;

Sima Dimitrijev, Nathan, AU;

Inventors:

Barry H. Harrison, Nathan, AU;

Sima Dimitrijev, Nathan, AU;

Assignee:

Griffith University, Nathan Queensland, AU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A one-transistor (1T) NVRAM cell that utilizes silicon carbide (SiC) to provide both isolation of non equilibrium charge, and fast and non destructive charging/discharging. To enable sensing of controlled resistance (and many memory levels) rather than capacitance, the cell incorporates a memory transistor that can be implemented in either silicon or Sic. The 1T cell has diode isolation to enable implementation of the architectures used in the present flash memories, and in particular the NOR and the NAND arrays. The 1T cell with diode isolation is not limited to SiC diodes. The fabrication method includes the step of forming a nitrided silicon oxide gate on the Sic substrate and subsequently carrying out the ion implantation and then finishing the formation of a self aligned MOSFET.


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