The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
Jun. 25, 2004
Yoshitaka Egawa, Yokohama, JP;
Yoriko Tanaka, Nagoya, JP;
Shinji Ohsawa, Ebina, JP;
Yukio Endo, Yokohama, JP;
Hiromi Kusakabe, Yokohama, JP;
Nagataka Tanaka, Yokohama, JP;
Yoshitaka Egawa, Yokohama, JP;
Yoriko Tanaka, Nagoya, JP;
Shinji Ohsawa, Ebina, JP;
Yukio Endo, Yokohama, JP;
Hiromi Kusakabe, Yokohama, JP;
Nagataka Tanaka, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki-shi, JP;
Abstract
In a CMOS image sensor, current leakage after a series of noise removing operations has been completed is suppressed in a read operation for each horizontal line, thereby suppressing image noise occurring on the output display screen of the image sensor. There are provided signal storage regions for storing the signals read from the unit cells in the same row selected in the imaging area onto vertical signal lines and horizontal select transistors for sequentially selecting and reading the signals stored in the individual signal storage regions and transferring them to read horizontal signal lines. At least in the period during which the signals are read from the signal storage regions, one of the drain and source of the transistor electrically connected to the signal path between the vertical signal line and horizontal signal line is biased in the reverse direction with respect to the substrate region. Two adjacent ones of the horizontal select transistors form a pair. The horizontal select transistors in each pair share one of the source/drain regions so as to be connected to the horizontal signal line in common, and the others of the source/drain regions are connected to the vertical signal line individually.