The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
May. 05, 2006
Tae-hyeong Park, Yongin-si, KR;
Kook-chul Moon, Yongin-si, KR;
Il-gon Kim, Seoul, KR;
Chul-ho Kim, Seoul, KR;
Kyung-hoon Kim, Uiwang-si, KR;
Ho-suk Maeng, Seoul, KR;
Tae-Hyeong Park, Yongin-si, KR;
Kook-Chul Moon, Yongin-si, KR;
Il-Gon Kim, Seoul, KR;
Chul-Ho Kim, Seoul, KR;
Kyung-Hoon Kim, Uiwang-si, KR;
Ho-Suk Maeng, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon-Si, KR;
Abstract
A level shifter and a display device having the same are provided. In a level shifter, a first transistor includes a gate electrode receiving a first driving voltage, and a source electrode receiving an input signal through an input terminal. A second transistor includes a drain electrode receiving the first driving voltage, and a source electrode electrically connected to a drain electrode of the first transistor through a first node. A third transistor includes a source electrode receiving a second driving voltage, a drain electrode electrically connected to a gate electrode of the second transistor through a second node, and a gate electrode receiving the input signal. A fourth transistor includes a drain electrode receiving the first driving voltage, a gate electrode electrically connected to the drain electrode of the first transistor through the first node, and a source electrode electrically connected to the drain electrode of the third transistor through the second node. An inverter inverts a signal outputted from the second node to apply the inverted signal to an output terminal.