The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2008
Filed:
Dec. 30, 2005
Gregory J. Dunn, Arlington Heights, IL (US);
Jaroslaw A. Magera, Palatine, IL (US);
Jovica Savic, Downers Grove, IL (US);
Gregory J. Dunn, Arlington Heights, IL (US);
Jaroslaw A. Magera, Palatine, IL (US);
Jovica Savic, Downers Grove, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A method is for fabricating an embedded capacitance printed circuit board assembly (). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (). Each capacitance structure () includes a crystallized dielectric oxide layer () sandwiched between an outer electrode layer () and an inner electrode layer () in which the two inner electrode layers are electrically connected together. A rivet via () and a stacked via () formed from a button via () and a stacked blind via () may be used to electrically connect the two inner electrode layers together. A spindle via () may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate () that includes two capacitance structures.