Methods of fabricating semiconductor memory devices including electrode contact structures having reduced contact resistance

Abstract

A semiconductor memory device includes a semiconductor substrate having an active region therein, an insulating layer on the substrate, and a lower electrode conductive pad extending through the insulating layer. The lower electrode conductive pad electrically contacts the active region at a lower surface of the lower electrode conductive pad. A lower electrode conductive plug on at least a portion of the lower electrode conductive pad electrically contacts the lower electrode conductive pad at an upper surface and at one sidewall thereof. The semiconductor device may further include a bitline conductor on the substrate adjacent the lower electrode conductive plug and an insulating spacer on a sidewall of the bitline conductor adjacent the lower electrode conductive plug. The insulating spacer may separate the lower electrode conductive plug from the bitline conductor by a distance sufficient to prevent electrical contact therebetween. Related methods are also discussed.