The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 15, 2008

Filed:

Apr. 05, 2006
Applicants:

Chi-hung Kao, Taipei, TW;

Chih-wei Chen, Taipei, TW;

Cheng-min Lin, Taipei, TW;

Yun-shan Chang, Taipei, TW;

Shyh-chyi Wong, Taipei, TW;

Inventors:

Chi-Hung Kao, Taipei, TW;

Chih-Wei Chen, Taipei, TW;

Cheng-Min Lin, Taipei, TW;

Yun-Shan Chang, Taipei, TW;

Shyh-Chyi Wong, Taipei, TW;

Assignee:

RichWave Technology Corp., NeiHu District, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A linearized bias circuit with adaptation resolves the problem happening to the power amplifier with conventional bias circuit that the DC and AC characteristics of the power amplifier shift or even deteriorate due to a temperature variation. The linearized bias circuit with adaptation has a reference voltage source, a first voltage source, a first resistor, a second resistor, a first NPN transistor, a second NPN transistor, and a third NPN transistor. The present invention has the characteristics of bias current temperature compensation, gain and phase compensations to achieve high linearity for the conventional power amplifier and reducing the DC consumption power. At the same time, the quantity of the required elements and layout area in the present invention are small so that the design complexity can be reduced for improving yield, reducing IC layout area, and reducing cost.


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