The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7358616 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 15, 2008

Filed:

Sep. 14, 2005
Applicants:

Syed M. Alam, Austin, TX (US);

Robert E. Jones, Austin, TX (US);

Scott K. Pozder, Austin, TX (US);

Inventors:

Syed M. Alam, Austin, TX (US);

Robert E. Jones, Austin, TX (US);

Scott K. Pozder, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.


Find Patent Forward Citations

Alam, Syed. (2008). Semiconductor stacked die/wafer configuration and packaging and method thereof (U.S. Patent No. 7358616). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7358616

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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