Flying-adder frequency synthesizer-based digital-controlled oscillator and video decoder including the same

Abstract

A video decoder () including a digital-control oscillator (DCO) () is disclosed. The DCO () includes a first flying-adder frequency synthesis circuit (S) that measures an input signal frequency, such as the horizontal sync frequency of an input video signal. A frequency control word (FREQ) is generated in response to this input signal frequency, and is applied to a second flying-adder frequency synthesis circuit (), which in turn selects the appropriate phases for leading and trailing edges of the output clock signal (PIX_CLK). Phase tuning of the output clock signal (PIX_CLK) can be effected by using an alternate flying-adder frequency synthesis circuit (') architecture, in combination with a phase signal (PH) generated by a digital controller (). Multiple phase-tuned sample clocks (PIX_CLK_A, PIX_CLK_B, PIX_CLK_C) can be similarly generated from multiple flying-adder frequency synthesis circuits (A,B,C), each controlled by the frequency control word (FREQ) and a corresponding phase signal (PHA, PHB, PHC). Video mode control logic () can also be implemented by way of a similar DCO architecture. The DCO () may be used to generate a clock signal at a large frequency multiple relative to the input signal, outside of the video decoder context.