Semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories)

Abstract

A semiconductor memory component and method for testing semiconductor memory components having a restricted memory area (partial good memories is disclosed. In one embodiment, in order to test the semiconductor memory components, test data are written to the memory cell array and, in parallel therewith, to a test write register. The data written to the memory cell array are compared bit by bit with the data stored in the test write register. An error free signal is generated in the case of matching. For semiconductor memory components classified as partial good memory, the result, independently of the result of the comparison for those data lines which are assigned to a memory area outside the functional memory area of the semiconductor memory component classified as partial good memory, is overwritten with an error free signal and a semiconductor memory component classified as all good memory is simulated. The testing of semiconductor memory components classified as partial good memory is accelerated and simplified.