The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2008
Filed:
Nov. 22, 2005
Floyd L. Dankert, Austin, TX (US);
Victor F. Andrade, Austin, TX (US);
Randal L. Posey, Austin, TX (US);
Michael K. Ciraula, Round Rock, TX (US);
Alexander W. Schaefer, Austin, TX (US);
Jerry D. Moench, Austin, TX (US);
Soolin Kao Chrudimsky, Austin, TX (US);
Michael C. Braganza, Austin, TX (US);
Jan Michael Huber, Austin, TX (US);
Amy M. Novak, Austin, TX (US);
Floyd L. Dankert, Austin, TX (US);
Victor F. Andrade, Austin, TX (US);
Randal L. Posey, Austin, TX (US);
Michael K. Ciraula, Round Rock, TX (US);
Alexander W. Schaefer, Austin, TX (US);
Jerry D. Moench, Austin, TX (US);
Soolin Kao Chrudimsky, Austin, TX (US);
Michael C. Braganza, Austin, TX (US);
Jan Michael Huber, Austin, TX (US);
Amy M. Novak, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.