The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2008
Filed:
Nov. 05, 2004
Jason R. Bergendahl, Sunnyvale, CA (US);
Ping-chen Liu, Fremont, CA (US);
Paul T. Sasaki, Sunnyvale, CA (US);
Suresh M. Menon, Sunnyvale, CA (US);
Atul V. Ghia, San Jose, CA (US);
Steven P. Young, Boulder, CO (US);
Trevor J. Bauer, Boulder, CO (US);
Jason R. Bergendahl, Sunnyvale, CA (US);
Ping-Chen Liu, Fremont, CA (US);
Paul T. Sasaki, Sunnyvale, CA (US);
Suresh M. Menon, Sunnyvale, CA (US);
Atul V. Ghia, San Jose, CA (US);
Steven P. Young, Boulder, CO (US);
Trevor J. Bauer, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Signal distribution of a regional signal is described. A programmable logic device includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distribution network. The regional signal distribution network is coupled to a configurable logic block via an interconnect tile. The regional buffer is coupled to a regional clock capable input/output block. Additionally described is a source synchronous interface for regional signal distribution.