The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2008
Filed:
Aug. 10, 2005
Parivallal Kannan, Longmont, CO (US);
Victor Z. Slonim, Broomfield, CO (US);
Salim Abid, Lafayette, CO (US);
Parivallal Kannan, Longmont, CO (US);
Victor Z. Slonim, Broomfield, CO (US);
Salim Abid, Lafayette, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of global clock placement for a circuit design to be implemented on a programmable logic device (PLD) can include identifying clock properties for the circuit design and identifying physical clock region attributes for the PLD. The method further can include specifying an Integer Linear Programming formulation (ILP) of a clock placement problem for the circuit design from the clock properties and the physical clock region attributes. The ILP formulation can be solved to determine whether a feasible clock placement exists for the circuit design.