The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2008

Filed:

Oct. 20, 2005
Applicants:

Daniel J. Barus, Glenham, NY (US);

Eileen M. Behrendt, Mahopac, NY (US);

Jeffrey R. Biamonte, Hyde Park, NY (US);

Raymond J. Harrington, Staatsburg, NY (US);

Timothy M. Trifilo, Walden, NY (US);

Inventors:

Daniel J. Barus, Glenham, NY (US);

Eileen M. Behrendt, Mahopac, NY (US);

Jeffrey R. Biamonte, Hyde Park, NY (US);

Raymond J. Harrington, Staatsburg, NY (US);

Timothy M. Trifilo, Walden, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.


Find Patent Forward Citations

Loading…