The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2008
Filed:
Jan. 13, 2005
Satya Prakash Arya, San Jose, CA (US);
John Thomas Contreras, Palo Alto, CA (US);
Klaas Berend Klaassen, Santa Jose, CA (US);
Nobumasa Nishiyama, Yokohama, JP;
Satya Prakash Arya, San Jose, CA (US);
John Thomas Contreras, Palo Alto, CA (US);
Klaas Berend Klaassen, Santa Jose, CA (US);
Nobumasa Nishiyama, Yokohama, JP;
Hitachi Global Storage Technologies Netherlands, B.V., Amsterdam, NL;
Abstract
A method and apparatus for reducing crosstalk and signal loss in an electrical interconnect is disclosed. The electrical interconnect includes a laminate. A plurality of signal traces and a subsequent plurality of traces are in a first formed layer of the laminate. The subsequent plurality of traces may be signal traces or power traces. The laminate has a dielectric layer between the first formed layer and a second formed layer. A plurality of serpentine patterns are in the second formed layer of the laminate. The plurality of serpentine patterns is separated from subsequent patterns. The plurality of serpentine patterns supports the plurality of signal traces and the subsequent plurality of patterns supports the subsequent plurality of traces. The supporting of the plurality of signal traces separate from the subsequent plurality of traces reduces write-to-read crosstalk and signal loss.