The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 01, 2008
Filed:
Jun. 22, 2005
Christopher A. Seams, Pleasanton, CA (US);
Yonghong Yang, Eden Prairie, MN (US);
Clifford P. Sandstrom, Lakeville, MN (US);
Prakash R. Krishanan, Milpitas, CA (US);
Christopher A. Seams, Pleasanton, CA (US);
Yonghong Yang, Eden Prairie, MN (US);
Clifford P. Sandstrom, Lakeville, MN (US);
Prakash R. Krishanan, Milpitas, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A method for arranging a semiconductor wafer within a photolithography tool and methods for processing a semiconductor wafer employing such an arrangement process are provided. The arrangement process includes positioning a semiconductor wafer on a stage in a pre-alignment unit of a photolithography tool such that a crystal orientation marker of the wafer is located at a first radial position. Thereafter, the wafer is moved to an exposure unit of the photolithography tool. During one or both of such steps, the semiconductor wafer is rotated such that the crystal orientation marker is relocated to a second, distinct radial position prior to arranging the wafer upon a stage of the exposure unit. In particular, the semiconductor wafer is rotated greater than approximately 10° and less than approximately 170° relative to the first radial position. The arrangement process is performed for lithography processes conducted during fabrication of a semiconductor device.