Dual port memory unit using a single port memory core

Abstract

A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).