The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2008

Filed:

Dec. 03, 2004
Applicants:

Sung-wei Lin, Plano, TX (US);

Sudhir K. Madan, Richardson, TX (US);

John Fong, Allen, TX (US);

Inventors:

Sung-Wei Lin, Plano, TX (US);

Sudhir K. Madan, Richardson, TX (US);

John Fong, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (, and) and columns (). A first conductor () is coupled to a plurality of the rows (, and) of memory cells. A first transistor () has a current path coupled between a voltage supply terminal () and the first conductor () and a control terminal coupled to receive a first control signal (PLV). A second transistor () has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).


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