The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2008

Filed:

Dec. 02, 2005
Applicants:

Kartik Nanda, Austin, TX (US);

Aryesh Amar, Austin, TX (US);

Rahul Singh, Austin, TX (US);

Jerome E Johnston, Austin, TX (US);

Inventors:

Kartik Nanda, Austin, TX (US);

Aryesh Amar, Austin, TX (US);

Rahul Singh, Austin, TX (US);

Jerome E Johnston, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.


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