The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7348734 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 25, 2008

Filed:

Jun. 30, 2005
Applicant:

Naveen Yadlapalli, Hoffman Estates, IL (US);

Inventor:

Naveen Yadlapalli, Hoffman Estates, IL (US);

Assignee:

Osram Sylvania Inc., Danvers, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05B 37/02 (2006.01); H05B 39/04 (2006.01); H05B 41/36 (2006.01); H02H 7/00 (2006.01); H02H 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method () for protecting a ballast from an output ground-fault condition includes the steps of applying power to the ballast (step), providing a startup delay period for a DC-to-DC converter (step), monitoring a voltage across a DC blocking capacitor (step), preventing startup of the DC-to-DC converter in response to the voltage across the DC blocking capacitor being greater than a threshold value during the startup delay period (step), and allowing startup of the DC-to-DC converter in response to the voltage across the DC blocking capacitor being less than the threshold value throughout the startup delay period (step). Preferably, the steps of monitoring (step), preventing (step), and allowing (step) are implemented by a microcontroller, and the DC-to-DC converter is preferably implemented as either a Sepic converter or a buck converter.


Find Patent Forward Citations

Loading…