The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2008

Filed:

Feb. 04, 2003
Applicants:

Michael S. Ball, La Mesa, CA (US);

Cristina N. Cifuentes, Atherton, CA (US);

David S. Allison, San Ramon, CA (US);

Liang T. Chen, Saratoga, CA (US);

Ankur Narang, New Delhi, IN;

Inventors:

Michael S. Ball, La Mesa, CA (US);

Cristina N. Cifuentes, Atherton, CA (US);

David S. Allison, San Ramon, CA (US);

Liang T. Chen, Saratoga, CA (US);

Ankur Narang, New Delhi, IN;

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for compiling a logic design includes inputting a logic design and an input file into a plurality of compilers, respectively, where the logic design comprises a plurality of modules, compiling separately the plurality of modules into a plurality of object files, and linking the plurality of object files to execute the logic design.


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