The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7346886 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 18, 2008

Filed:

Apr. 12, 2005
Applicants:

Youzou Fukagawa, Tochigi-ken, JP;

Mario Nakamori, Yokohama, JP;

Inventors:

Youzou Fukagawa, Tochigi-ken, JP;

Mario Nakamori, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In determining a relative position between a chip lattice including rectangular cells, each of which has a size of a chip to be formed on a substrate and an effective area on the substrate, one representative cell in the chip lattice is divided into a plurality of partial areas in accordance with an existing area, of a representative point of the effective area, in which chip sets trimmed from the chip lattice with the effective area are identical. A partial area corresponding to a chip set including a maximum number of chips is specified from the plurality of partial areas, and the representative point is set in the specified partial area.


Find Patent Forward Citations

Fukagawa, Youzou. (2008). Method and apparatus for determining chip arrangement position on substrate (U.S. Patent No. 7346886). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7346886

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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