The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2008
Filed:
Mar. 23, 2006
Milind P. Padhye, Austin, TX (US);
Darrell L. Carder, Dripping Springs, TX (US);
Bhoodev Kumar, Austin, TX (US);
Bart J. Martinec, Austin, TX (US);
Milind P. Padhye, Austin, TX (US);
Darrell L. Carder, Dripping Springs, TX (US);
Bhoodev Kumar, Austin, TX (US);
Bart J. Martinec, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.